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分频器VHDL描述
- 在数字电路中，常需要对较高频率的时钟进行分频操作，得到较低频率的时钟信号。我们知道，在硬件电路设计中时钟信号时非常重要的。-in digital circuits, the need for regular high frequency clock operating frequency for hours, a lower frequency of the clock signal. We know that the hardware circuit design clock signal i
8倍频vhdl
- 该文件可用vhdl语言实现时钟8倍频，运行环境可在maxplus2和ise的仿真软件上-the document available VHDL Language 8 clock frequency, the operating environment and ideally maxplus2 simulation software
muxplusii --vhdl 经典程序
- 用VHDL编写的数字时钟,可变宽度脉冲产生器-prepared using VHDL digital clock, Variable width pulse generator, etc.
CK20-VHDL
- 经典ＣＫ２０时钟程序，实现了时钟的时，分，秒记数，并可以重调，置０-classic procedures CK20 clock and realized the clock, minute and second count, and can be re-emphasize that the Home 0
clockbyvhdl
- 在xilinx的ise环境下用vhdl编写的一个时钟程序。-in the environment and ideally with the preparation of a VHDL clock procedures.
VHDL.sheji.2
- 电子时钟VHDL程序与仿真 10进制计数器设计与仿真 6进制计数器设计与仿真-electronic clock procedures and VHDL simulation Decimal counter design and simulation of six NUMBER Design and Simulation
LED.VHDL
- LED控制VHDL程序与仿真 分别介绍采用FPGA对LED进行静态和动态显示的数字时钟控制程序-LED control procedures and VHDL simulation briefed on the use of FPGA LED static and dynamic significantly the figures show clock control procedures
UP3_CLOCK
- 用vhdl编写的时钟 主要实现了时钟功能时间调教功能有待实现 -prepared using VHDL clock main function of clock time tuning function to be achieved
VHDL
- vhdl 电子时钟源代码 全部。 所有模块 的设计 及其代码描述。 可以用来参考设计，使用-vhdl clock Electronic clock all the source code.
vhdl-clock-with-vga-output-for-Nexys-2
- Vhdl code for a working digital clock which can be displayed on a vga screen. The clock can be set using a single pushbutton. This project was written for nexys 2 board but can be easily ported to any other fpga using vhdl.
clock
- 这个程序的主要内容是基于VHDl的时钟方面的编程设计-The main content of this program is based VHDl clock programming design
VHDL Digital Clock
- A digital stop watch designed in VHDL
VHDL-clock
- 用VHDL写的数字钟程序，能够实现显示时分秒，时间可以调节，还能设定闹钟-Written in VHDL,the digital clock procedures can display every minute, the time can be adjusted, but also to set the alarm
clock
- there's a clock divider for DE2 altra board clock (50MHz)
clock
- 数字钟可以实现整点响铃，预置数，十二小时24小时切换(Digital clock can achieve the whole point of the bell)
world-clock
- 世界时钟，用vhdl语言编辑的一个世界时钟，基本入门编程(World clock, using a VHDL language editor of a world clock, basic entry programming)
clock
- 数字时钟，用VHDL语言设计，能调时间，整点响铃(Digital clock, designed in VHDL language, can adjust the time, the whole bell ring)
clock
- VHDL实现时钟功能，异步清零，其余161实现技术功能。(VHDL realizes clock function, asynchronous zero, and the other 161 technology functions.)
clock
- 用VHDL完成的数字钟设计。可选24h与12h两种时制，运用到按键消抖。(The digital clock is designed with VHDL. Optional 24h and 12h two kinds of time system, apply to the button to shake.)
vhdl编程电子钟
- 实现24小时，可以整点报时的电子钟，使用TEC-8实验台(An electronic clock that can be used for 24 hours, using the TEC-8 test platform)